A 3.6-ns ECL field programmable array logic deviceMILLHOLLAN, M. S; CHIAKANG SUNG.IEEE journal of solid-state circuits. 1985, Vol 20, Num 5, pp 1036-1042, issn 0018-9200Article

ECL40 technology: speed and complexity projectionsHAWKER, I.British Telecom technology journal. 1985, Vol 3, Num 1, pp 70-78, issn 0265-0193Article

A table reduction technique for logarithmically architected digital filtersFREY, M. L; TAYLOR, F. J.IEEE transactions on acoustics, speech, and signal processing. 1985, Vol 33, Num 3, pp 718-719, issn 0096-3518Article

A subnanosecond 5-kbit bipolar ECL RAMCHING-TE CHUANG; TANG, D. D; LI, G. P et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1265-1267, issn 0018-9200Article

High-speed bipolar ECL RAM seriesOGIUE, K; IWABUCHI, M; TONOMURA, K et al.Hitachi review. 1985, Vol 34, Num 6, pp 299-304, issn 0018-277XArticle

A subnanosecond 2000 gate array with ECL 100K comptabilitySATO, F; TAKAHASHI, T; MISAWA, H et al.IEEE journal of solid-state circuits. 1984, Vol 19, Num 1, pp 5-9, issn 0018-9200Article

Clock breakthrough in ECL integrated circuitsHAWKER, I.IEE proceedings. Part G. Electronic circuits and systems. 1983, Vol 130, Num 6, pp 252-256, issn 0143-7089Article

D-flip-flop with a programmable delay with power consumption for implementation in smart sensorsRUTKA, M. J; WOLFFENBUTTEL, R. F.Sensors and actuators. A, Physical. 1993, Vol 37-38, pp 600-606, issn 0924-4247Conference Paper

Speech analysis and synthesis methods developed at ECL in NTT-from LPC to LSPSUGAMURA, N; ITAKURA, F.Speech communication. 1986, Vol 5, Num 2, pp 199-215, issn 0167-6393Article

Comparison of five high speed bistables by computer simulationRUSS, D. M; FAULKNER, D. W.IEE proceedings. Part I. Solid-state and electron devices. 1985, Vol 132, Num 5, pp 210-216, issn 0143-7100Article

Entwurf einer integrierten 16×16-Koppelmatrix mit geringem Leistungsverbrauch für eine Bitrate von 280 Mbit/s = Conception d'une matrice de couplage 16×16 avec faible consommation pour un débit de 280 Mbit/s = Design of an integrated 16×16 crosspoint assay with low power consumption for a bit rate of 280 Mbit/sREIN, H.-M.AEU. Archiv für Elektronik und Übertragungstechnik. 1984, Vol 38, Num 6, pp 345-354, issn 0001-1096Article

An 8-ns 256K ECL SRAM with CMOS memory array and battery backup capabilityVAN TRAN, H; SCOTT, D. B; PAK KUEN FUNG et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1041-1047, issn 0018-9200Article

A double-word-line structure in bipolar ECL random access memoryKAYANO, S; ANAMI, K; NAKASE, Y et al.IEEE journal of solid-state circuits. 1987, Vol 22, Num 4, pp 543-547, issn 0018-9200Article

Logic array design for 250 MHzOBERMEIER, W.IEEE transactions on industrial electronics (1982). 1986, Vol 33, Num 4, pp 355-360, issn 0278-0046Article

A 400-gate ECL gate array: MB 12K series LSIOHNO, K.-I; TAKEDA, H; MASUNAGA, H et al.Fujitsu scientific and technical journal. 1985, Vol 21, Num 3, pp 330-336, issn 0016-2523Article

Advances in bipolar VLSIWILSON, G. R.Proceedings of the IEEE. 1990, Vol 78, Num 11, pp 1707-1719, issn 0018-9219Article

Minimisation technique for series-gated emitter-coupled logicCHOY, C. S; JONES, P. L.IEE proceedings. Part G. Electronic circuits and systems. 1989, Vol 136, Num 3, pp 105-113, issn 0143-7089, 9 p.Article

A 4.5 ns access time 1 K×4 Bit ECL RAMNOKUBO, J; TAMURA, T; NAKAMAE, M et al.IEEE journal of solid-state circuits. 1983, Vol 18, Num 5, pp 515-520, issn 0018-9200Article

Fault modelling of ECL devicesMENON, S. M; JAYASUMANA, A. P; MALAIYA, Y. K et al.Electronics Letters. 1990, Vol 26, Num 15, pp 1105-1108, issn 0013-5194Article

A 0.85-ns 1-kbit ECL RAMMIYANAGA, H; KONAKA, S; KOBAYASHI, Y et al.IEEE journal of solid-state circuits. 1986, Vol 21, Num 4, pp 501-504, issn 0018-9200Article

Circuit de synchronisation en réseau prédiffusé ECL 100 K utilisant le principe de la justification positive = Synchronisation circuit with prediffused network ECL 100 K using the principle of positive justificationDANIEL, R; LE MORZADEC, Y; MAHEO, P et al.1985, 6 p.Report

ECL fault modellingMORANDI, C; NICCOLAI, L; FANTINI, F et al.IEE proceedings. Part E. Computers and digital techniques. 1988, Vol 135, Num 6, pp 312-317, issn 0143-7062Article

Formal hadware verification methodology and its application to a network interface chipGORDON, M. J. C; HERBERT, J.IEE proceedings. Part E. Computers and digital techniques. 1986, Vol 133, Num 5, pp 255-270, issn 0143-7062Article

Sub-nanosecond ECL uncommitted cell array for transmission system applicationsHAWKER, I; SHEPPARD, M. J; SCOTT, D. L et al.IEE proceedings. Part G. Electronic circuits and systems. 1985, Vol 132, Num 2, pp 60-63, issn 0143-7089Article

IBM enterprise system/9000 type 9121 system controller and memory subsystem designCURRAN, B. W; WALZ, M. H.IBM journal of research and development. 1991, Vol 35, Num 3, pp 357-366, issn 0018-8646Article